Boundary Scan and Build-In Self-Test Circuitry Generation
碩士 === 國立清華大學 === 電機工程研究所 === 82 === In this thesis, we review IEEE Boundary Scan (BS) Std. 1149.1-1990 and Boundary Scan Description Lan- guage (BSDL), and discuss boundary scan generation methodology. We develop a CAD tool (BS-BIST genera...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1994
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| Online Access: | http://ndltd.ncl.edu.tw/handle/63175925710361764121 |