| Summary: | 碩士 === 國立清華大學 === 資訊科學學系 === 82 === The relationship between some techniques for sequential logic
synthesis (i.e., retiming and peripheral retiming) and high-
level synthesis (i.e., pipelining and loop folding) are studied
in this paper. We prove that the problem of loop folding is
equivalent to that of the combination of retiming and
pipelining; the result of peripheral retiming can be
accomplished by extensive retiming, or by loop folding. This
discovery makes it possible to exchange the techniques
developed previously for these two problems and, hence, cross-
fertilize both areas. To show the usefulness of this discovery,
we propose an algorithm, based on the relationship, for
minimizing the clock period of sequential circuits. The
proposed algorithm provides not only further insight into
retiming but also a much greater area/speed design tradeoff
opportunity compared with that of using retiming alone. The
experimental results on a set of benchmarks indicate that the
proposed algorithm is 2-order faster than Saxe's relaxation
algorithm implemented in the SIS package.
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