A Study on the Relationship Between Retiming and Loop Folding
碩士 === 國立清華大學 === 資訊科學學系 === 82 === The relationship between some techniques for sequential logic synthesis (i.e., retiming and peripheral retiming) and high- level synthesis (i.e., pipelining and loop folding) are studied in this paper. We...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1994
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| Online Access: | http://ndltd.ncl.edu.tw/handle/54125532956290839280 |