A parallel-pattern parallel-fault fault simulation engine for synchronous sequential circuits
碩士 === 國立交通大學 === 電子研究所 === 82 === In this thesis, we represents a parallel-pattern parallel- fault hardware accelerator for the zero delay fault simulation for the gate level synchronous sequential circuit. A novel parallel sequence fault...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1994
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| Online Access: | http://ndltd.ncl.edu.tw/handle/44534475061220759235 |