Performance Optimization of Sequential Circuits
碩士 === 國立成功大學 === 電機工程研究所 === 82 === In this thesis, a new sequential circuit delay optimi- zation technique based on both I/O retiming and logic transformation is proposed. I/O retiming is a relaxing retiming which retimes all...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1994
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| Online Access: | http://ndltd.ncl.edu.tw/handle/54792392147598813516 |