Custom DSP Architecture for VSELP Speech Coding Algorithm
碩士 === 國立交通大學 === 電子研究所 === 81 === The main topic for this thesis is our implementation of an 8Kbps Vector Sum-Excited Linear Prediction (VSELP) speech CODEC (encoder and decoder). Meanwhile, we intent to implement it as a low-power-consump...
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1993
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| Online Access: | http://ndltd.ncl.edu.tw/handle/65615217914675514538 |
| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 81 === The main topic for this thesis is our implementation of an
8Kbps Vector Sum-Excited Linear Prediction (VSELP) speech CODEC
(encoder and decoder). Meanwhile, we intent to implement it as
a low-power-consumption ASIC instead of utilizing the existing
general purpose DSP chips. We are also going to describe the
VSELP algorithm and the custom processor architecture which we
developed. Furthermore, we will describe the instruction set of
this processor and the simulation result of this architecture
with assembly codes for VSELP is also included.
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