Custom DSP Architecture for VSELP Speech Coding Algorithm
碩士 === 國立交通大學 === 電子研究所 === 81 === The main topic for this thesis is our implementation of an 8Kbps Vector Sum-Excited Linear Prediction (VSELP) speech CODEC (encoder and decoder). Meanwhile, we intent to implement it as a low-power-consump...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
1993
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| Online Access: | http://ndltd.ncl.edu.tw/handle/65615217914675514538 |