Characterization and Design Guidelines of Submicron LATID (LArge Tilt-angle Implanted Drain) MOS Devices

• Main Authors: Peng-Cheng Chou, 周鵬程
• Other Authors: Steve S.Chung
• Format: Others
• Language: en_US
• Online Access: http://ndltd.ncl.edu.tw/handle/02576611738309258353

碩士 === 國立交通大學 === 電子研究所 === 81 === In recent years, various drain structures have been widely ed to alleviate the hot electron effect in submicron MOS devices. Conventional LDD MOS device which has a partial- overlap drain structure, has an inherent spacer - induced degradation. New overlapped structure devices such as the LATID (LArge-Tilt- angle Implanted Drain) devices have been developed as such a need to avoid the spacer-induced degradation and to improve the device performance. Here, studies will be focused on optimization of a In this thesis, first a simulation environment using process, device and circuit simulation in coupled form is developed. The process (SUPREM IV) and device (PISCES-2B) simulators have been modified and calibrated against the current 0.7um LATID MOS devices by adjusting physical parameters such as those in 2-D doping profile, mobility model and the impact ionization so that experimental verification of the simulated drain and substrate current can be justified. Then, the optimum design for a 0.6um n-channel LATID device with effective gate length 0.3um can be achieved. Here, an experimental design method which is the so called Response Surface Method (RSM) is used for a scaled device design. At the same time, the design guidelines for the LATID device are also provided in this thesis. LATID MOS device has larger current drivability and higher circuit switching speed. But LATID suffers more short channel effect induced threshold voltage lowering and has higher source -and-drain series resistance. These two properties and the lower punchthrough voltage which may put a limit on its application to the future deep-submicron ULSI design.