Study of the retrograde-well CMOS Using High-energy Ion Implantation

• Main Authors: Yaw-Kuang Wu, 吳燿光
• Other Authors: Kow-Ming Chang, Sun-Chieh Chien
• Format: Others
• Language: en_US
• Published: 1993
• Online Access: http://ndltd.ncl.edu.tw/handle/07690603680059596740

碩士 === 國立交通大學 === 電子研究所 === 81 === The retrograde-well process using high energy ion implantation for CMOS technology has been proposed to instead of the conventional diffusion well. The high-energy ion implantation technology eliminates the need for process time at high temperature. This increase the packing density and the flexibility in device design. In this thesis, the retrograde P- well using single charged ion implantation and the retrograde N- well using double charged ion implantation are implemented in CMOS devices. The vertical isolation between the N+ diffusion and the N-substrate for retrograde P-well and the field isolation offered by the retrograde well without additional field implant can be also obtained with an acceptable level. The LATID process for NMOS devices and pocket implant process for PMOS devices are compared and addressed. Furthermore, the CMOS devices characteristics including narrow width effect, body effect, latchup, and device reliability are also discussed. It is found that 0.5um NMOS device created in retrograde pwell with lower implant dose(2.6E13cm-2) LATID and higher concentration retrograde well(180keV implant energy and 1E13 cm-2 implant dose) shows the better turn off effect for 3.3V operation. However, it suffers from more serious "spacer induced degradation". For 0.6um PMOS device created in retrograde nwell, the condition of 360keV implant energy and 2E12cm-2 implant dosage shows the better turen off characteristics and field isolation effect.