VLSI Design of the Cepstrum and Bayesian Network Chips for Speech Recognition System
碩士 === 國立成功大學 === 電機工程研究所 === 81 === There are two main topics in this thesis, one is the VLSI implementation for the LPC cepstrum algorithm, and the other is to present two VLSI architectures for implementing the Bayesian Network. In the f...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1993
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| Online Access: | http://ndltd.ncl.edu.tw/handle/01833046255106461687 |