An efficient timing model for CMOS bistable latch

An efficient timing model for CMOS bistable latch

碩士 === 大同工學院 === 電機工程研究所 === 75 ===

Bibliographic Details
Main Authors:	CHEN, JUN-JIE, 陳俊傑
Other Authors:	GUO, MING-YAN
Format:	Others
Language:	zh-TW
Published:	1987
Online Access:	http://ndltd.ncl.edu.tw/handle/54938466530048596529

Internet

http://ndltd.ncl.edu.tw/handle/54938466530048596529