Direct Synthesis of Netlists into Pre-routed FPGAs
This thesis introduces a new approach to compilation for FPGAs, which we call direct synthesis. We take a technology-mapped circuit netlist and directly map it into a pre-placed and routed FPGA overlay. Solving this problem may help to address the increasing portion of compile time that is attribute...
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| Language: | en_ca |
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2014
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| Online Access: | http://hdl.handle.net/1807/65549 |