An FPGA-based Accelerator Platform for Network-on-chip Simulation
The increased demand for on-chip communication bandwidth as a result of the multi-core trend has made packet-switched networks-on-chip (NoCs) a more compelling choice for the communication backbone in next-generation systems. NoC designs are sensitive to many design parameters—hence the study of new...
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| Language: | en_ca |
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2010
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| Online Access: | http://hdl.handle.net/1807/25504 |