Code optimizations for narrow bitwidth architectures
This thesis takes a HW/SW collaborative approach to tackle the problem of computational inefficiency in a holistic manner. The hardware is redesigned by restraining the datapath to merely 16-bit datawidth (integer datapath only) to provide an extremely simple, low-cost, low-complexity execution core...
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| Format: | Doctoral Thesis |
| Language: | English |
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Universitat Politècnica de Catalunya
2012
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| Online Access: | http://hdl.handle.net/10803/96190 |