Reusing cached schedules in an out-of-order processor with in-order issue logic
Modern processors use out-of-order processing logic to achieve high performance in Instructions Per Cycle (IPC) but this logic has a serious impact on the achievable frequency. In order to get better performance out of smaller transistors there is a trend to increase the number of cores per die inst...
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| Format: | Doctoral Thesis |
| Language: | English |
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Universitat Politècnica de Catalunya
2011
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| Online Access: | http://hdl.handle.net/10803/80536 |