Reducing DRAM Row Activations with Eager Writeback
This thesis describes and evaluates a new approach to optimizing DRAM performance and energy consumption that is based on eagerly writing dirty cache lines to DRAM. Under this approach, dirty cache lines that have not been recently accessed are eagerly written to DRAM when the corresponding row has...
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| Format: | Others |
| Language: | English |
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2012
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| Online Access: | http://hdl.handle.net/1911/64701 |