30 GHZ adaptive receiver equalization design using 28 nm CMOS technology
<p> This thesis consists of a 28 nm submicron circuit design for high speed transceiver circuits used in high-speed wireline communications that operate in the 60 Gb/s range. This thesis is based on research done on high speed equalizer standards for the USB 3.1 SuperSpeed Differential Channe...
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| Language: | EN |
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San Jose State University
2015
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| Online Access: | http://pqdtopen.proquest.com/#viewpdf?dispub=1594420 |