Design methodology for low-jitter phase-locked loops
This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise simulation with the behavioral model is roughly 310 times f...
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| Language: | en_US |
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2012
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| Online Access: | http://hdl.handle.net/1957/32786 |