Performance enhancement techniques for low power digital phase locked loops

Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increas...

Full description

Bibliographic Details
Main Author:	Elshazly, Amr
Other Authors:	Hanumolu, Pavan Kumar
Language:	en_US
Published:	2012
Subjects:	Phase locked loops Delay locked loops Supply noise mitigation background calibration Digital PLL Supply noise Time to digital converter TDC Switched ring oscillator SRO-TDC Digital circuits Low power Area efficient Digitally controlled oscillator Performance enhancement techniques Integrated circuits Frequency synthesizers Clock multipliers Microelectronics Analog and mixed Circuits and systems Analog Digital Solid state circuit Phase-locked loops Electronic noise > Prevention Low voltage systems
Online Access:	http://hdl.handle.net/1957/31116

id	ndltd-ORGSU-oai-ir.library.oregonstate.edu-1957-31116
record_format	oai_dc
spelling	ndltd-ORGSU-oai-ir.library.oregonstate.edu-1957-311162012-07-17T03:34:26ZPerformance enhancement techniques for low power digital phase locked loopsElshazly, AmrPhase locked loopsDelay locked loopsSupply noise mitigationbackground calibrationDigital PLLSupply noiseTime to digital converterTDCSwitched ring oscillatorSRO-TDCDigital circuitsLow powerArea efficientDigitally controlled oscillatorPerformance enhancement techniquesIntegrated circuitsFrequency synthesizersClock multipliersIntegrated circuitsMicroelectronicsAnalog and mixedCircuits and systemsAnalogDigitalSolid state circuitPhase-locked loopsElectronic noise -- PreventionLow voltage systemsFrequency synthesizersDesire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions. In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques.Graduation date: 2013Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014Hanumolu, Pavan Kumar2012-07-16T21:59:29Z2012-06-182012-06-182014-07-16Thesis/Dissertationhttp://hdl.handle.net/1957/31116en_US
collection	NDLTD
language	en_US
sources	NDLTD
topic	Phase locked loops Delay locked loops Supply noise mitigation background calibration Digital PLL Supply noise Time to digital converter TDC Switched ring oscillator SRO-TDC Digital circuits Low power Area efficient Digitally controlled oscillator Performance enhancement techniques Integrated circuits Frequency synthesizers Clock multipliers Integrated circuits Microelectronics Analog and mixed Circuits and systems Analog Digital Solid state circuit Phase-locked loops Electronic noise -- Prevention Low voltage systems Frequency synthesizers
spellingShingle	Phase locked loops Delay locked loops Supply noise mitigation background calibration Digital PLL Supply noise Time to digital converter TDC Switched ring oscillator SRO-TDC Digital circuits Low power Area efficient Digitally controlled oscillator Performance enhancement techniques Integrated circuits Frequency synthesizers Clock multipliers Integrated circuits Microelectronics Analog and mixed Circuits and systems Analog Digital Solid state circuit Phase-locked loops Electronic noise -- Prevention Low voltage systems Frequency synthesizers Elshazly, Amr Performance enhancement techniques for low power digital phase locked loops
description	Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions. In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques. === Graduation date: 2013 === Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014
author2	Hanumolu, Pavan Kumar
author_facet	Hanumolu, Pavan Kumar Elshazly, Amr
author	Elshazly, Amr
author_sort	Elshazly, Amr
title	Performance enhancement techniques for low power digital phase locked loops
title_short	Performance enhancement techniques for low power digital phase locked loops
title_full	Performance enhancement techniques for low power digital phase locked loops
title_fullStr	Performance enhancement techniques for low power digital phase locked loops
title_full_unstemmed	Performance enhancement techniques for low power digital phase locked loops
title_sort	performance enhancement techniques for low power digital phase locked loops
publishDate	2012
url	http://hdl.handle.net/1957/31116
work_keys_str_mv	AT elshazlyamr performanceenhancementtechniquesforlowpowerdigitalphaselockedloops
_version_	1716392573510090752

Performance enhancement techniques for low power digital phase locked loops

Similar Items