Performance enhancement techniques for low power digital phase locked loops

Performance enhancement techniques for low power digital phase locked loops

Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increas...

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Bibliographic Details
Main Author: Elshazly, Amr
Other Authors: Hanumolu, Pavan Kumar
Language:en_US
Published: 2012
Subjects:
Phase locked loops
Delay locked loops
Supply noise mitigation
background calibration
Digital PLL
Supply noise
Time to digital converter
TDC
Switched ring oscillator
SRO-TDC
Digital circuits
Low power
Area efficient
Digitally controlled oscillator
Performance enhancement techniques
Integrated circuits
Frequency synthesizers
Clock multipliers
Microelectronics
Analog and mixed
Circuits and systems
Analog
Digital
Solid state circuit
Phase-locked loops
Electronic noise > Prevention
Low voltage systems
Online Access:http://hdl.handle.net/1957/31116

Internet

http://hdl.handle.net/1957/31116

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