Exploiting thread-level parallelism on reconfigurable architectures: a cross-layer approach.

• Online Access: http://hdl.handle.net/2047/D20254348

Field Programmable Gate Arrays (FPGAs) are one major class of architectures commonly used in parallel computing systems. FPGAs provide a massive number (i.e., millions) programmable logic blocks and I/O cells, as well as programmable interconnects, which can be configured for a particular application. This reconfigurable architecture is flexible and power efficient, and potentially, provides better floating-point operations per watt rates versus general purpose architectures, such as CPUs and GPUs. However, programming an FPGA can be challenging and time-consuming, requiring hardware description language (HDL) experience and digital design expertise. High-level synthesis (HLS) tools have been designed to ease the FPGA programming task by generating HDL (e.g., Verilog or VHDL) codes from high-level languages (e.g., C/C++, OpenCL). Inparticular, there have been recent developments in OpenCL-based HLS tools (OpenCL-HLS) to enable programmers to construct a customized data-path that can best match a parallel application, relieving the programmer of many implementation details.