Optimization of power and delay in VLSI circuits using transistor sizing and input ordering

Optimization of power and delay in VLSI circuits using transistor sizing and input ordering

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994. === Includes bibliographical references (p. 85-88). === by Chin Hwee Tan. === M.S.

Bibliographic Details
Main Author: Tan, Chin Hwee
Other Authors: Jonathan Allen.
Format: Others
Language:English
Published: Massachusetts Institute of Technology 2007
Subjects:
Electrical Engineering and Computer Science
Online Access:http://hdl.handle.net/1721.1/35979

Internet

http://hdl.handle.net/1721.1/35979

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