A model for analysis of the effects of redundancy and error correction on DRAM memory yield and reliability
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000. === This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. === Includes bibliographical refe...
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| Format: | Others |
| Language: | English |
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Massachusetts Institute of Technology
2006
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| Online Access: | http://hdl.handle.net/1721.1/32094 |