A partitioning framework for distributed verilog simulation /

• Main Author: Huang, Hai, 1974-
• Other Authors: Tropper, Carl (advisor)
• Format: Others
• Language: en
• Published: McGill University 2003
• Subjects: Computer Science.
• Online Access: http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=80291

The HDL (Hardware Description Language) helps designers of modern digital systems to compete with the increasing size and complexity of VLSI circuits. Simulation is usually used for verification in the design process, which tends to be a bottleneck. Distributed simulation on a network of workstations tries to provide a cost-effective solution. The partitioning of the circuit is a critical factor to the performance of the distributed simulation. === This study presents the design and implementation of a partitioning framework which is incorporated into the DVS (Distribute Verilog Simulator) framework. A number of well-known partitioning algorithms are implemented including a new algorithm CAKE. The classical FM and popular CLIP algorithms and their recursive bisection version are implemented. The partitioning results are studied for large circuits in ISPD98 benchmark suite. The effect of partitioning results on the performance of the distributed simulation is analyzed with a multiplier circuit in ISCAS85.