Dynamically Reconfigurable Active Cache Modeling
This thesis presents a novel dynamically reconfigurable active L1 instruction and data cache model, called DRAC. Employing cache, particularly L1, can speed up memory accesses, reduce the effects of memory bottleneck and consequently improve the system performance; however, efficient design of a cac...
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2014
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| Online Access: | http://spectrum.library.concordia.ca/978188/1/Barzegar_MASc_S2014.pdf Barzegar, Ali <http://spectrum.library.concordia.ca/view/creators/Barzegar=3AAli=3A=3A.html> (2014) Dynamically Reconfigurable Active Cache Modeling. Masters thesis, Concordia University. |