Visible synchronization based cache coherence
In large scale machines, thousands of processor cycles, in other words, missed opportunities to issue floating point instructions, may be lost while waiting for a high latency synchronization or memory operation to complete, or a stall in an instruction pipeline to be dealt with. Latency is avoided...
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| Format: | Others |
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1997
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| Online Access: | http://spectrum.library.concordia.ca/273/1/MQ44885.pdf Kumar, Krishna <http://spectrum.library.concordia.ca/view/creators/Kumar=3AKrishna=3A=3A.html> (1997) Visible synchronization based cache coherence. Masters thesis, Concordia University. |