Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder

Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder

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In this thesis, we present an FPGA implementation of parallel-node low-density-parity-check convolutional-code (PN-LDPC-CC) encoder and decoder. A 2.4 Gbit/s rate-1/2 (3, 6) PN-LDPC-CC encoder and decoder were implemented on an Altera development and education board (DE4). Detailed power measurement...

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Bibliographic Details
Main Author: Li, Si-Yun
Language:en
Published: 2012
Subjects:
LDPC
FPGA
Convolutional Codes
FEC
Electrical and Computer Engineering
Online Access:http://hdl.handle.net/10012/6962

Internet

http://hdl.handle.net/10012/6962

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