Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters

Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters

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Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum sampling frequency allows for an overall sampling frequency of M times the individual converters' sampling rate. However,...

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Bibliographic Details
Main Author: Shirtliff, Jason Neil
Language:en
Published: 2010
Subjects:
analog circuit design
timing mismatches
interleaved analog to digital converters
microelectronics
Electrical and Computer Engineering
Online Access:http://hdl.handle.net/10012/5523

Internet

http://hdl.handle.net/10012/5523

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