Statistical Yield Analysis and Design for Nanometer VLSI

Statistical Yield Analysis and Design for Nanometer VLSI

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Process variability is the pivotal factor impacting the design of high yield integrated circuits and systems in deep sub-micron CMOS technologies. The electrical and physical properties of transistors and interconnects, the building blocks of integrated circuits, are prone to significant variations...

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Bibliographic Details
Main Author: Jaffari, Javid
Language:en
Published: 2010
Subjects:
Yield
Process Variation
VLSI
SRAM
Digital
Analog
CMOS
Variance Reduction
Quasi Monte Carlo
Latin Hypercube Sampling
Adaptive Sampling
Thermal Analysis
Leakage Power
Electrical and Computer Engineering
Online Access:http://hdl.handle.net/10012/5361

Internet

http://hdl.handle.net/10012/5361

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