Bimodal Gate Oxide Breakdown in Sub-100 nm CMOS Technology

Bimodal Gate Oxide Breakdown in Sub-100 nm CMOS Technology

Show other versions (1)

In the last three decades, the electronic industry has registered a tremendous progress. The continuous and aggressive downsizing of the transistor feature sizes (CMOS scaling) has been the main driver of the astonishing growth and advancement of microelectronic industry. Currently, the CMOS scaling...

Full description

Bibliographic Details
Main Author: Rezaee, Leila
Language:en
Published: 2008
Subjects:
Oxide Breakdown
Percolation
CMOS
TDDB
CVS
CCS
SILC
Stress Induced Leakage Current
Markov Chain
Noise
Post-breakdown Current
Soft Breakdown
Hard Breakdown
Weibull
Critical Phenomenon
Quasi-critical Phenomenon
Analytical
Percolation Probability
Reliability
Monte-Carlo
Electrical and Computer Engineering
Online Access:http://hdl.handle.net/10012/4155

Internet

http://hdl.handle.net/10012/4155

Similar Items