Design of Variation-Tolerant Circuits for Nanometer CMOS Technology: Circuits and Architecture Co-Design

Design of Variation-Tolerant Circuits for Nanometer CMOS Technology: Circuits and Architecture Co-Design

Show other versions (1)

Aggressive scaling of CMOS technology in sub-90nm nodes has created huge challenges. Variations due to fundamental physical limits, such as random dopants fluctuation (RDF) and line edge roughness (LER) are increasing significantly with technology scaling. In addition, manufacturing tolerances in pr...

Full description

Bibliographic Details
Main Author: Abu-Rahma, Mohamed Hassan
Language:en
Published: 2008
Subjects:
SRAM
yield
statistical
low-power
variability
withi-die variaitons
bitcell
stability
static noise margin
delay variation
Electrical and Computer Engineering
Online Access:http://hdl.handle.net/10012/4119

Internet

http://hdl.handle.net/10012/4119

Similar Items