Concurrent Error Detection in Finite Field Arithmetic Operations

With significant advances in wired and wireless technologies and also increased shrinking in the size of VLSI circuits, many devices have become very large because they need to contain several large units. This large number of gates and in turn large number of transistors causes the devices to be mo...

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Main Author: Bayat Sarmadi, Siavash
Language:en
Published: 2008
Subjects:
Online Access:http://hdl.handle.net/10012/3460
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spelling ndltd-LACETR-oai-collectionscanada.gc.ca-OWTU.10012-34602013-10-04T04:08:13ZBayat Sarmadi, Siavash2008-01-03T16:23:59Z2008-01-03T16:23:59Z2008-01-03T16:23:59Z2007http://hdl.handle.net/10012/3460With significant advances in wired and wireless technologies and also increased shrinking in the size of VLSI circuits, many devices have become very large because they need to contain several large units. This large number of gates and in turn large number of transistors causes the devices to be more prone to faults. These faults specially in sensitive and critical applications may cause serious failures and hence should be avoided. On the other hand, some critical applications such as cryptosystems may also be prone to deliberately injected faults by malicious attackers. Some of these faults can produce erroneous results that can reveal some important secret information of the cryptosystems. Furthermore, yield factor improvement is always an important issue in VLSI design and fabrication processes. Digital systems such as cryptosystems and digital signal processors usually contain finite field operations. Therefore, error detection and correction of such operations have become an important issue recently. In most of the work reported so far, error detection and correction are applied using redundancies in space (hardware), time, and/or information (coding theory). In this work, schemes based on these redundancies are presented to detect errors in important finite field arithmetic operations resulting from hardware faults. Finite fields are used in a number of practical cryptosystems and channel encoders/decoders. The schemes presented here can detect errors in arithmetic operations of finite fields represented in different bases, including polynomial, dual and/or normal basis, and implemented in various architectures, including bit-serial, bit-parallel and/or systolic arrays.enconcurrent error detection (CED)Finite field operationspolynomial basisdual basisnormal basissystolic arraysConcurrent Error Detection in Finite Field Arithmetic OperationsThesis or DissertationElectrical and Computer EngineeringDoctor of PhilosophyElectrical and Computer Engineering
collection NDLTD
language en
sources NDLTD
topic concurrent error detection (CED)
Finite field operations
polynomial basis
dual basis
normal basis
systolic arrays
Electrical and Computer Engineering
spellingShingle concurrent error detection (CED)
Finite field operations
polynomial basis
dual basis
normal basis
systolic arrays
Electrical and Computer Engineering
Bayat Sarmadi, Siavash
Concurrent Error Detection in Finite Field Arithmetic Operations
description With significant advances in wired and wireless technologies and also increased shrinking in the size of VLSI circuits, many devices have become very large because they need to contain several large units. This large number of gates and in turn large number of transistors causes the devices to be more prone to faults. These faults specially in sensitive and critical applications may cause serious failures and hence should be avoided. On the other hand, some critical applications such as cryptosystems may also be prone to deliberately injected faults by malicious attackers. Some of these faults can produce erroneous results that can reveal some important secret information of the cryptosystems. Furthermore, yield factor improvement is always an important issue in VLSI design and fabrication processes. Digital systems such as cryptosystems and digital signal processors usually contain finite field operations. Therefore, error detection and correction of such operations have become an important issue recently. In most of the work reported so far, error detection and correction are applied using redundancies in space (hardware), time, and/or information (coding theory). In this work, schemes based on these redundancies are presented to detect errors in important finite field arithmetic operations resulting from hardware faults. Finite fields are used in a number of practical cryptosystems and channel encoders/decoders. The schemes presented here can detect errors in arithmetic operations of finite fields represented in different bases, including polynomial, dual and/or normal basis, and implemented in various architectures, including bit-serial, bit-parallel and/or systolic arrays.
author Bayat Sarmadi, Siavash
author_facet Bayat Sarmadi, Siavash
author_sort Bayat Sarmadi, Siavash
title Concurrent Error Detection in Finite Field Arithmetic Operations
title_short Concurrent Error Detection in Finite Field Arithmetic Operations
title_full Concurrent Error Detection in Finite Field Arithmetic Operations
title_fullStr Concurrent Error Detection in Finite Field Arithmetic Operations
title_full_unstemmed Concurrent Error Detection in Finite Field Arithmetic Operations
title_sort concurrent error detection in finite field arithmetic operations
publishDate 2008
url http://hdl.handle.net/10012/3460
work_keys_str_mv AT bayatsarmadisiavash concurrenterrordetectioninfinitefieldarithmeticoperations
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