A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS

A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS

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This thesis proposes a decision-feedback equalizer (DFE) scheme for blind ADC-based receivers to overcome the challenges introduced by blind sampling. It presents the design, simulation, and implementation of a 5Gb/s speculative DFE for a 2x blind ADC-based receiver. The complete receiver, including...

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Bibliographic Details
Main Author: Sarvari, Siamak
Other Authors: Sheikholeslami, Ali
Language:en_ca
Published: 2010
Subjects:
high-speed signaling
decision-feedback equalizer (DFE)
blind sampling
ADC-based receiver
speculative
look-ahead
clock and data recovery (CDR)
blind oversampling
CMOS
jitter tolerance
eye diagram
equalizer
0544
Online Access:http://hdl.handle.net/1807/29987

Internet

http://hdl.handle.net/1807/29987

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