Parallelizing Simulated Annealing Placement for GPGPU
Field Programmable Gate Array (FPGA) devices are increasing in capacity at an exponential rate, and thus there is an increasingly strong demand to accelerate simulated annealing placement. Graphics Processing Units (GPUs) offer a unique opportunity to accelerate this simulated annealing placement on...
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| Language: | en_ca |
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2010
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| Online Access: | http://hdl.handle.net/1807/25456 |