| Summary: | Field-Programmable Gate Arrays (FPGAs) consume roughly 14 times more dynamic power than Application Specific Integrated Circuits (ASICs) making it challenging to incorporate FPGAs in low-power applications. To bridge the gap, power consumption in FPGAs needs to be addressed at the application, Computer-Aided Design (CAD) tool, architecture, and circuit levels. The ability to properly evaluate proposals to reduce the power dissipation of FPGAs requires a realistic and accurate experimental framework. Mature FPGA power models are flexible, but can suffer from poor accuracy due to estimations on signal activity and simplifications. Additionally, run-time increases with the size of the design. Other techniques use unrealistic assumptions while physically measuring the power of a circuit running on an FPGA. Neither of these techniques can accurately portray the power consumption of FPGA circuits.
We propose a framework to allow FPGA researchers to evaluate the impact of proposals for the reduction of power in FPGAs. The framework consists of a real-world System-on-Chip (SoC) and can be used to explore algorithmic and CAD
techniques, by providing the ability to measure the power at run-time. High-level access to common low-level power-management techniques, such as clock gating, Dynamic Frequency Scaling (DFS), and Dynamic Partial Reconfiguration (DPR),
is provided. We demonstrate our framework by evaluating the effects of pipelining and DPR on power. We also reason why our framework is necessary by showing that it provides different conclusions than that of previous work.
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