FPGA emulation for critical-path coverage analysis
A major task in post-silicon validation is timing validation: it can be incredibly difficult to ensure a new chip meets timing goals. Post-silicon validation is the first opportunity to check timing with real silicon under actual operating conditions and workloads. However, post-silicon tests suffer...
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| Language: | English |
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University of British Columbia
2012
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| Online Access: | http://hdl.handle.net/2429/43426 |