Test and fault-tolerance for network-on-chip infrastructures
The demands of future computing, as well as the challenges of nanometer-era VLSI design, will require new design techniques and design styles that are simultaneously high performance, energy-efficient, and robust to noise and process variation. One of the emerging problems concerns the communication...
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| Format: | Others |
| Language: | English |
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University of British Columbia
2008
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| Online Access: | http://hdl.handle.net/2429/2816 |