On-chip surfing interconnect
With growing chip sizes and operating frequencies, on-chip global interconnect has become a critical bottleneck for CMOS technology. With processes scaling into deep submicron scales, the gap between gate delay and global-interconnect delay increases with each technology generation. Bandwidth is al...
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| Language: | English |
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University of British Columbia
2010
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| Online Access: | http://hdl.handle.net/2429/23597 |