Power Optimal Network-On-Chip Interconnect Design

Power Optimal Network-On-Chip Interconnect Design

A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Hence, techniques to reduce...

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Bibliographic Details
Main Author: Vikas, G
Other Authors: Varghese, Kuruvilla
Language:en_US
Published: 2011
Subjects:
Network On Chip - Design and Construction
Electric Power Networks
Application Specific System On Chip
Routers (Computer Networks)
Chip Multi Core Processor
Network-on-Chip Interconnect Design
Computer Engineering
Online Access:http://etd.iisc.ernet.in/handle/2005/1408
http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf

Internet

http://etd.iisc.ernet.in/handle/2005/1408
http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf

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