Process Variability-Aware Performance Modeling In 65 nm CMOS

Process Variability-Aware Performance Modeling In 65 nm CMOS

With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss....

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Bibliographic Details
Main Author: Harish, B P
Other Authors: Bhat, Navakanta
Language:en_US
Published: 2011
Subjects:
Complementary Metal Oxide Semiconductors
Semiconductors
NAND Gate
Gate Delay Models
CMOS Digital Circuits
Circuit Design
Circuit Delay Performance
Circuit Delay Distribution
CMOS Designs
65nm CMOS
Electronic Engineering
Online Access:http://hdl.handle.net/2005/1080

Internet

http://hdl.handle.net/2005/1080

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