Modelagem e validação de redes intrachip através de síntese comportamental
Made available in DSpace on 2013-08-07T18:42:35Z (GMT). No. of bitstreams: 1 000402108-Texto+Completo-0.pdf: 3755135 bytes, checksum: 7d348d529638f63dbd140311e4213857 (MD5) Previous issue date: 2008 === The growing demand for system-on-Chip (SoC) time-to-market reduction leads to relevant changes...
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| Language: | Portuguese |
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Pontifícia Universidade Católica do Rio Grande do Sul
2013
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| Online Access: | http://hdl.handle.net/10923/1502 |