Uma abordagem para suporte à verificação funcional no nível de sistema aplicada a circuitos digitais que empregam a Técnica Power Gating.
Submitted by Johnny Rodrigues (johnnyrodrigues@ufcg.edu.br) on 2018-11-07T17:16:29Z No. of bitstreams: 1 GEORGE SOBRAL SILVEIRA - TESE PPGEE 2012..pdf: 4756019 bytes, checksum: 743307d8794218c3a447296994c05332 (MD5) === Made available in DSpace on 2018-11-07T17:16:29Z (GMT). No. of bitstreams: 1 GEO...
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| Language: | Portuguese |
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Universidade Federal de Campina Grande
2012
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| Online Access: | http://dspace.sti.ufcg.edu.br:8080/jspui/handle/riufcg/2146 |