O efeito da largura de Fetch no desempenho das arquiteturas super escalar, trace cache e DTSVLIW
Made available in DSpace on 2016-12-23T14:33:33Z (GMT). No. of bitstreams: 1 dissertacao.pdf: 525748 bytes, checksum: d81fee4d754843c091457bdd3b0ce230 (MD5) Previous issue date: 2003-10-29 === Superscalar machines fetch multiple scalar instructions per cycle from the instruction cache. However, ma...
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| Format: | Others |
| Language: | Portuguese |
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Universidade Federal do Espírito Santo
2016
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| Online Access: | http://repositorio.ufes.br/handle/10/6349 |