Uma arquitetura para verificação de blocos de computação gráfica em hardware
=== This work presents, analyzes and validates a novel verication architecture for computer graphics cores. This architecture has four stages and it is supported by two techniques: the automatic verication and the high and low level verication. The rst stage denesand implements a high level executa...
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| Format: | Others |
| Language: | Portuguese |
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Universidade Federal de Minas Gerais
2005
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| Online Access: | http://hdl.handle.net/1843/SLBS-6GUPEC |