Efficient graph algorithm execution on data-parallel architectures

Efficient graph algorithm execution on data-parallel architectures

Mechanisms for improving the execution efficiency of graph algorithms on Data-Parallel Architectures were proposed and identified. Execution of graph algorithms on GPGPU architectures, the prevalent data-parallel architectures was considered. Irregular and data dependent accesses in graph algorithms...

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Bibliographic Details
Main Author: Bangalore Lakshminarayana, Nagesh
Other Authors: Kim, Hyesoon
Format: Others
Language:en_US
Published: Georgia Institute of Technology 2015
Subjects:
Graph algorithms
Data-parallel architectures
GPGPU architectures
Prefetching
Cache hierarchy
Inclusion property
Cache bypass
Fine-grained accesses
BFS characterization
Online Access:http://hdl.handle.net/1853/53058

Internet

http://hdl.handle.net/1853/53058

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