The System-on-a-Chip Lock Cache
In this dissertation, we implement efficient lock-based synchronization by a novel, high performance, simple and scalable hardware technique and associated software for a target shared-memory multiprocessor System-on-a-Chip (SoC). The custom hardware part of our solution is provided in the form of a...
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| Format: | Others |
| Language: | en_US |
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Georgia Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1853/5253 |