Designing low power SRAM system using energy compression

Designing low power SRAM system using energy compression

The power consumption in commercial processors and application specific integrated circuits increases with decreasing technology nodes. Power saving techniques have become a first class design point for current and future VLSI systems. These systems employ large on-chip SRAM memories. Reducing memor...

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Bibliographic Details
Main Author: Nair, Prashant
Published: Georgia Institute of Technology 2013
Subjects:
Computer architecture
Leakage reduction
SRAM
VLSI
Low power
Random access memory
Image processing Digital techniques
Digital video
Online Access:http://hdl.handle.net/1853/47663

Internet

http://hdl.handle.net/1853/47663

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