An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices

This thesis presents methods for developing FPGA-based test solutions that solve the challenges of evaluating source-synchronous and protocol-laden systems and devices at multi-gigabit per second signaling rates. These interfaces are becoming more prevalent in emerging designs and are difficult to...

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Main Author: Gray, Carl Edward
Published: Georgia Institute of Technology 2012
Subjects:
Online Access:http://hdl.handle.net/1853/44858
id ndltd-GATECH-oai-smartech.gatech.edu-1853-44858
record_format oai_dc
spelling ndltd-GATECH-oai-smartech.gatech.edu-1853-448582013-01-07T20:39:33ZAn fpga based architecture for native protocol testing of multi-gbps source-synchronous devicesGray, Carl EdwardTest architectureDigital systemsHigh-speedField programmable gate arraysGigabit communicationsDigital communications TestingComputer networks TestingThis thesis presents methods for developing FPGA-based test solutions that solve the challenges of evaluating source-synchronous and protocol-laden systems and devices at multi-gigabit per second signaling rates. These interfaces are becoming more prevalent in emerging designs and are difficult to test using traditional automated test equipment (ATE) and test instrumentation which were designed for testing designs utilizing synchronous and deterministic signaling. The main motivation of this research was to develop solutions that address these challenges. The methods shown in this thesis are used to design a test architecture consisting of custom hardware components, reprogrammable digital logic for hardware integration, and a software interface for external data transport and configuration. The hardware components consist of a multi-GHz field programmable gate array (FPGA) based interface board providing processing, control, and data capabilities to the system and enhanced by one or more application modules which can be tailored for specific test functionality compatible with source-synchronous and protocol interfaces. Software controls from a host computer provide high and low level access to the internal tester data and configuration memory space. The architecture described in this thesis is demonstrated through a specific test solution for a high-speed optical packet switched network called the Data Vortex. Reprogrammable firmware and software controls allow for a high degree of adaptability and application options. The modularized implementation of the hardware elements introduces additional adaptability and future upgradability, capable of incorporating new materials and design techniques for the test platform and application modules.Georgia Institute of Technology2012-09-20T18:22:18Z2012-09-20T18:22:18Z2012-07-03Dissertationhttp://hdl.handle.net/1853/44858
collection NDLTD
sources NDLTD
topic Test architecture
Digital systems
High-speed
Field programmable gate arrays
Gigabit communications
Digital communications Testing
Computer networks Testing
spellingShingle Test architecture
Digital systems
High-speed
Field programmable gate arrays
Gigabit communications
Digital communications Testing
Computer networks Testing
Gray, Carl Edward
An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices
description This thesis presents methods for developing FPGA-based test solutions that solve the challenges of evaluating source-synchronous and protocol-laden systems and devices at multi-gigabit per second signaling rates. These interfaces are becoming more prevalent in emerging designs and are difficult to test using traditional automated test equipment (ATE) and test instrumentation which were designed for testing designs utilizing synchronous and deterministic signaling. The main motivation of this research was to develop solutions that address these challenges. The methods shown in this thesis are used to design a test architecture consisting of custom hardware components, reprogrammable digital logic for hardware integration, and a software interface for external data transport and configuration. The hardware components consist of a multi-GHz field programmable gate array (FPGA) based interface board providing processing, control, and data capabilities to the system and enhanced by one or more application modules which can be tailored for specific test functionality compatible with source-synchronous and protocol interfaces. Software controls from a host computer provide high and low level access to the internal tester data and configuration memory space. The architecture described in this thesis is demonstrated through a specific test solution for a high-speed optical packet switched network called the Data Vortex. Reprogrammable firmware and software controls allow for a high degree of adaptability and application options. The modularized implementation of the hardware elements introduces additional adaptability and future upgradability, capable of incorporating new materials and design techniques for the test platform and application modules.
author Gray, Carl Edward
author_facet Gray, Carl Edward
author_sort Gray, Carl Edward
title An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices
title_short An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices
title_full An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices
title_fullStr An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices
title_full_unstemmed An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices
title_sort fpga based architecture for native protocol testing of multi-gbps source-synchronous devices
publisher Georgia Institute of Technology
publishDate 2012
url http://hdl.handle.net/1853/44858
work_keys_str_mv AT graycarledward anfpgabasedarchitecturefornativeprotocoltestingofmultigbpssourcesynchronousdevices
AT graycarledward fpgabasedarchitecturefornativeprotocoltestingofmultigbpssourcesynchronousdevices
_version_ 1716475776734330880