An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices

An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices

This thesis presents methods for developing FPGA-based test solutions that solve the challenges of evaluating source-synchronous and protocol-laden systems and devices at multi-gigabit per second signaling rates. These interfaces are becoming more prevalent in emerging designs and are difficult to...

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Bibliographic Details
Main Author: Gray, Carl Edward
Published: Georgia Institute of Technology 2012
Subjects:
Test architecture
Digital systems
High-speed
Field programmable gate arrays
Gigabit communications
Digital communications Testing
Computer networks Testing
Online Access:http://hdl.handle.net/1853/44858

Internet

http://hdl.handle.net/1853/44858

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