Learning, probabilistic, and asynchronous technologies for an ultra efficient datapath
A novel microarchitecture and circuit design techniques are presented for an asynchronous datapath that not only exhibits an extremely high rate of performance, but is also energy efficient. A 0.5 um chip was fabricated and tested that contains test circuits for the asynchronous datapath. Results...
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Georgia Institute of Technology
2010
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| Online Access: | http://hdl.handle.net/1853/31724 |